Espressif Systems

2025-08 to 2026-01

SystemVerilog
Synopsys Design Compiler

Digital IC Design Intern

Digital IC Design internship at Espressif Systems, Pudong, Shanghai, from August 2025 to January 2026. Worked with SystemVerilog and Synopsys Design Compiler.

On-site periods:

  1. 17 Aug to 11 Sep: Singapore
  2. 14 Sep to 26 Nov: Shanghai
  3. 1 Dec to 30 Jan: Singapore