CG3207 RISC-V CPU
2025-11-03
RISC-V
CPU
FPGA
Verilog
Computer Architecture
Linux
School Project
DIY RISC-V CPU implementation with comprehensive features including atomics, interrupts, Control and Status Registers (CSRs), a bootloader CPU core, and direct mapped cache.
Features
- RISC-V ISA Support: Full implementation of RISC-V instruction set architecture
- Atomics: Support for atomic operations
- Interrupts: Interrupt handling capabilities
- CSRs: Control and Status Registers implementation
- Bootloader CPU Core: Dedicated bootloader CPU core for system initialization
- Direct Mapped Cache: Cache implementation for improved performance
- Linux Compatibility: Tested with Linux 6.5.2 kernel (with varying Results)
This project demonstrates a complete CPU implementation from scratch, showcasing understanding of computer architecture, processor design, and system-level programming.
Check it out!